diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index a61f75b..c028e5e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -41,8 +41,8 @@
 /* 1 second delay should be plenty of time for block reset. */
 #define	RESET_MAX_TIMEOUT	1000000
 
-#define	MX28_BLOCK_SFTRST	(1 << 31)
-#define	MX28_BLOCK_CLKGATE	(1 << 30)
+#define	MXS_BLOCK_SFTRST	(1 << 31)
+#define	MXS_BLOCK_CLKGATE	(1 << 30)
 
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 inline void lowlevel_init(void) {}
@@ -81,7 +81,7 @@
 #endif
 }
 
-int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == mask)
@@ -92,7 +92,7 @@
 	return !timeout;
 }
 
-int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == 0)
@@ -103,34 +103,34 @@
 	return !timeout;
 }
 
-int mx28_reset_block(struct mxs_register_32 *reg)
+int mxs_reset_block(struct mxs_register_32 *reg)
 {
 	/* Clear SFTRST */
-	writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
 
-	if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
 		return 1;
 
 	/* Clear CLKGATE */
-	writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
 
 	/* Set SFTRST */
-	writel(MX28_BLOCK_SFTRST, &reg->reg_set);
+	writel(MXS_BLOCK_SFTRST, &reg->reg_set);
 
 	/* Wait for CLKGATE being set */
-	if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
 		return 1;
 
 	/* Clear SFTRST */
-	writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
 
-	if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
 		return 1;
 
 	/* Clear CLKGATE */
-	writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
 
-	if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
 		return 1;
 
 	return 0;
@@ -229,7 +229,7 @@
 		get_cpu_type(),
 		get_cpu_rev(),
 		mxc_get_clock(MXC_ARM_CLK) / 1000000);
-	printf("BOOT:  %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
+	printf("BOOT:  %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
 	return 0;
 }
 #endif
@@ -299,7 +299,7 @@
 
 	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
 
-	if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
 				MXS_OCOTP_MAX_TIMEOUT)) {
 		printf("MXS FEC: Can't get MAC from OCOTP\n");
 		return;
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 84d4a17..ddafddb 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -82,9 +82,9 @@
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
 
-	for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) {
-		masked = bootmode & mx28_boot_modes[i].boot_mask;
-		if (masked == mx28_boot_modes[i].boot_pads)
+	for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
+		masked = bootmode & mxs_boot_modes[i].boot_mask;
+		if (masked == mxs_boot_modes[i].boot_pads)
 			break;
 	}
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index c4b0f5e..4ed75e6 100644
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -66,7 +66,7 @@
 		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
 
 	/* Reset Timers and Rotary Encoder module */
-	mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
+	mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
 
 	/* Set fixed_count to 0 */
 	writel(0, &timrot_regs->hw_timrot_fixed_count0);
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 91645eb..9d1e599 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 MX28 specific functions
+ * Freescale i.MX233/i.MX28 specific functions
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -20,14 +20,14 @@
  *
  */
 
-#ifndef __MX28_H__
-#define __MX28_H__
+#ifndef __SYS_PROTO_H__
+#define __SYS_PROTO_H__
 
-int mx28_reset_block(struct mxs_register_32 *reg);
-int mx28_wait_mask_set(struct mxs_register_32 *reg,
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
 		       uint32_t mask,
 		       int timeout);
-int mx28_wait_mask_clr(struct mxs_register_32 *reg,
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
 		       uint32_t mask,
 		       int timeout);
 
@@ -39,13 +39,13 @@
 			const unsigned int iomux_size);
 #endif
 
-struct mx28_pair {
+struct mxs_pair {
 	uint8_t	boot_pads;
 	uint8_t boot_mask;
 	const char *mode;
 };
 
-static const struct mx28_pair mx28_boot_modes[] = {
+static const struct mxs_pair mxs_boot_modes[] = {
 	{ 0x00, 0x0f, "USB #0" },
 	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
 	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
@@ -69,6 +69,6 @@
 	uint32_t	mem_dram_size;
 };
 
-int mx28_dram_init(void);
+int mxs_dram_init(void);
 
-#endif	/* __MX28_H__ */
+#endif	/* __SYS_PROTO_H__ */
diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c
index 87f3f35..5a1042e 100644
--- a/board/bluegiga/apx4devkit/apx4devkit.c
+++ b/board/bluegiga/apx4devkit/apx4devkit.c
@@ -130,7 +130,7 @@
 
 	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
 
-	if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
 		MXS_OCOTP_MAX_TIMEOUT)) {
 		printf("MXS: Can't get serial number from OCOTP\n");
 		return;
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 38eff4f..ca5a32f 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -512,7 +512,7 @@
 	if (ret)
 		return ret;
 
-	if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
+	if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
 				1 << chan, timeout)) {
 		ret = -ETIMEDOUT;
 		mxs_dma_reset(chan);
@@ -557,7 +557,7 @@
 	struct mxs_apbh_regs *apbh_regs =
 		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 
-	mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
+	mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
 
 #ifdef CONFIG_APBH_DMA_BURST8
 	writel(APBH_CTRL0_AHB_BURST8_EN,
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index 5d61d7a..2a193c2 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -41,7 +41,7 @@
 	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 	int ret;
 
-	ret = mx28_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
+	ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
 	if (ret) {
 		debug("MXS I2C: Block reset timeout\n");
 		return;
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 018939f..9a98c6b 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -336,7 +336,7 @@
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 
 	/* Reset SSP */
-	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
+	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 
 	/* 8 bits word length in MMC mode */
 	clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 807c9fd..bf9414f 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -237,7 +237,7 @@
 	int timeout = MXS_NAND_BCH_TIMEOUT;
 	int ret;
 
-	ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
+	ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
 		BCH_CTRL_COMPLETE_IRQ, timeout);
 
 	writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
@@ -972,7 +972,7 @@
 	uint32_t tmp;
 
 	/* Configure BCH and set NFC geometry */
-	mx28_reset_block(&bch_regs->hw_bch_ctrl_reg);
+	mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
 
 	/* Configure layout 0 */
 	tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
@@ -1080,7 +1080,7 @@
 	}
 
 	/* Reset the GPMI block. */
-	mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
+	mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
 
 	/*
 	 * Choose NAND mode, set IRQ polarity, disable write protection and
diff --git a/drivers/rtc/mxsrtc.c b/drivers/rtc/mxsrtc.c
index 72f7400..ffefb91 100644
--- a/drivers/rtc/mxsrtc.c
+++ b/drivers/rtc/mxsrtc.c
@@ -41,7 +41,7 @@
 	 * is taken from the linux kernel driver for the STMP37xx RTC since
 	 * documentation doesn't mention it.
 	 */
-	ret = mx28_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg,
+	ret = mxs_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg,
 		0x80 << RTC_STAT_STALE_REGS_OFFSET, MXS_RTC_MAX_TIMEOUT);
 
 	if (ret)
@@ -80,7 +80,7 @@
 	mxs_rtc_set_time(0);
 
 	/* Reset the RTC block */
-	ret = mx28_reset_block(&rtc_regs->hw_rtc_ctrl_reg);
+	ret = mxs_reset_block(&rtc_regs->hw_rtc_ctrl_reg);
 	if (ret)
 		printf("MXS RTC: Block reset timeout\n");
 }
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index bd834fb..a037c13 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -139,7 +139,7 @@
 	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 	uint32_t reg = 0;
 
-	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
+	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 
 	writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
 
@@ -193,7 +193,7 @@
 
 		writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
 
-		if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
+		if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
 			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 			printf("MXS SPI: Timeout waiting for start\n");
 			return -ETIMEDOUT;
@@ -205,7 +205,7 @@
 		writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
 
 		if (!write) {
-			if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
+			if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
 				SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
 				printf("MXS SPI: Timeout waiting for data\n");
 				return -ETIMEDOUT;
@@ -215,7 +215,7 @@
 			data++;
 		}
 
-		if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
+		if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
 			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 			printf("MXS SPI: Timeout waiting for finish\n");
 			return -ETIMEDOUT;